Analysis of Scheduling and Memory Access Delays in Multicores

Analysis of Scheduling and Memory Access Delays in Multicores

A SimEvents Model for the Analysis of Scheduling and Memory Access Delays in Multicores
This project present how to integrate architectural properties using SimEvents to introduce scheduling and memory contention delays in a Simulink model. The model consist of periodic and sporadic tasks executed on an architectural platform of four symmetric cores connected to local- and global memories. The model is AUTOSAR compatible, where the task execute a set of runnables whom communicate be means of labels. We also provide the implementation for four memory access patterns: AUTOSAR implicit- and explicit communication, a pattern providing data consistency throughout the execution of a task and last, the LET execution model.

The package provides three models. First, an automotive benchmark provided by Bosch for the waters challenge is modeled [1]. This model consist of 21 tasks, 1250 runnables and 10000 labels. The second model consist of a simple example of three tasks, executed by one core. This model provides a mapping between the architectural and function model, where the 3 tasks are associated with 1 runnable each. The runnables are mapped to invoke a function Simulink model consisting of three servos. Last, a periodic and all preemptive Waters challenge inspired model is provided to illustrate the advantages of using the LET paradigm.

[1] A Hamann et al. “FMTV 2016 verification challenge”. In: Inf Process Lett (2016).