Demo design and files from the webinar "Improve RTL verification by connecting to MATLAB", which shows:
* SystemVerilog DPI component generation from MATLAB for stimulus and checking functions
* Integration of the generated components into a SystemVerilog UVM test environment
* Importing handwritten Verilog into HDL Verifier cosimulation
* Debugging the testbench using by cosimulating Simulink with Mentor Graphics Questa
This download includes the slides from the webinar, with the demo instructions interleaved. The slides also cover how advanced customers perform verification and validation at the model level to shift verification to earlier in the workflow.
Jack Erickson (2020). Connect RTL verification to MATLAB (https://www.mathworks.com/matlabcentral/fileexchange/70303-connect-rtl-verification-to-matlab), MATLAB Central File Exchange. Retrieved .