Mixed-Signal Blockset
Design, analyze, and simulate analog and mixed-signal systems
Mixed-Signal Blockset™ provides models of components and impairments, analysis tools, and test benches for designing and verifying mixed-signal integrated circuits (ICs).
You can model PLLs, data converters, and other systems at different levels of abstraction. These models can be used to simulate mixed-signal components together with complex DSP algorithms and control logic. You can customize models to include impairments such as noise, nonlinearity, jitter, and quantization effects. Rapid system-level simulation using variable-step Simulink® solvers lets you debug the implementation and identify design flaws without simulating the IC at the transistor level.
With the Mixed-Signal Analyzer app you can analyze, identify trends in, and visualize mixed-signal data. The Cadence Virtuoso ADE MATLAB Integration option lets you import databases of circuit-level simulation results into MATLAB®. Alternatively, you can import a SPICE netlist and create or modify a linear, time-invariant circuit with parasitic elements extracted from the IC design. The blockset provides analysis functions for post- processing simulation results to verify specifications, fit characteristics, and report measurements.
Get Started:
Mixed-Signal Analyzer App
Use the Mixed-Signal Analyzer app to interactively visualize, analyze, and identify trends in mixed-signal data in the time and frequency domains.
The Cadence Virtuoso ADE MATLAB Integration option lets you import databases of circuit-level transient, AC, and DC, simulation results into MATLAB.
Cadence Virtuoso ADE database imported into the Mixed-Signal Analyzer app.
PLL Design
Design and simulate phase-locked loops (PLLs) at the system level. Typical architectures include integer-N PLLs with single or dual modulus prescalers, and fractional-N PLLs with accumulators or delta-sigma modulators. Verify and visualize the open-loop and closed-loop response of your designs.
ADC and DAC Design
Design and simulate analog-to-digital (ADC) and digital-to-analog (DAC) data converters at the system level. Typical architectures include flash and successive approximation register (SAR) ADCs as well as binary weighted and segmented DACs.
SAR ADC with Time Scope.
Building Blocks Library
Design your mixed-signal system using building blocks such as charge pumps, loop filters, phase frequency detectors (PFDs), voltage-controlled oscillators (VCOs), clock dividers, and sampling clock sources, among others. You can further refine analog models at a lower abstraction level with Simscape Electrical™.
PLL building blocks library.
Import SPICE netlists
You can import a SPICE netlist and create or modify a linear, time-invariant circuit with parasitic elements extracted from the IC design using the Linear Circuit Wizard block.
Third-order passive loop filter SPICE netlist and resulting transfer function.
Timing Imperfections
Model rise and fall times, finite slew rates, and variable time delays in your feedback loops. With the timing effects modeled, you can run simulations to assess stability and estimate lock times.
Phase Noise and Jitter
Model aperture jitter in ADCs and specify arbitrary phase noise profiles in the frequency domain for VCOs and PLLs. Visualize the effects with the Eye Diagram block.
Power spectrum and phase noise profile for a VCO.
Testbenches
Measure the lock time, phase noise profile, and operating frequency of PLLs, and characterize the performance of building blocks such as VCOs, PFDs, and charge pumps. Measure AC and DC characteristics and aperture jitter of ADCs.
ADC testbench for measuring DC and AC performance.
Integration with IC Simulation Environments
Reuse system-level mixed-signal models in your IC design environment via cosimulation or by generating a SystemVerilog module using HDL Verifier™. For the digital part of your system you can generate synthesizable HDL code using HDL Coder™.
