Mixed-Signal Blockset
Design and simulate analog and mixed-signal systems
Mixed-Signal Blockset™ provides models of components and impairments, analysis tools, and test benches for designing and verifying mixed-signal integrated circuits (ICs).
You can model PLLs, data converters, and other systems at different levels of abstraction and explore a range of IC architectures. You can customize models to include impairments such as noise, nonlinearity, and quantization effects, and refine the system description using a top-down methodology.
Using the test benches provided, you can verify system performance and improve modeling fidelity by fitting measurement characteristics or circuit-level simulation results. Rapid system-level simulation using variable-step Simulink® solvers lets you debug the implementation and identify design flaws before simulating the IC at the transistor level.
With Mixed-Signal Blockset you can simulate mixed-signal components together with complex DSP algorithms and control logic. As a result, both analog and digital design teams can work from the same executable specification.
Get Started:
PLL Design
Design and simulate phase-locked loops (PLLs) at the system level. Typical architectures include integer-N PLLs with single or dual modulus prescalers, and fractional-N PLLs with accumulators or delta-sigma modulators. Verify and visualize the open-loop and closed-loop response of your design.
Fractional-N PLL with a delta-sigma modulator.
ADC Design
Design and simulate analog-to-digital data converters (ADCs) at the system level, including timing and quantization impairments. Typical architectures include flash and Successive Approximation Register (SAR) ADCs.
SAR ADC with Time Scope.
Building Blocks Library
Design your mixed-signal system using building blocks such as charge pumps, loop filters, phase frequency detectors (PFDs), voltage-controlled oscillators (VCOs), clock dividers, and sampling clock sources, among others. You can further refine analog models at a lower abstraction level with Simscape Electrical™.
PLL building blocks library.
Timing Imperfections
Model rise and fall times, finite slew rates, and variable time delays in your feedback loops. With the timing effects modeled, you can run simulations to assess stability and estimate lock times.
Jitter effects on a clock signal.
Phase Noise and Jitter
Model aperture jitter in ADCs and specify arbitrary phase noise profiles in the frequency domain for VCOs and PLLs. Visualize the effects with the Eye Diagram scope.
Phase noise profile for a VCO.
Test Benches
Measure the lock time, phase noise profile, and operating frequency of PLLs, and characterize the performance of building blocks such as VCOs, PFDs, and charge pumps. Measure AC and DC characteristics and aperture jitter of ADCs.
ADC test bench.
Integration with IC Simulation Environments
Reuse system-level mixed-signal models in your IC design environment via cosimulation or by generating a SystemVerilog module using HDL Verifier™ . For the digital part of your system you can generate synthesizable HDL code using HDL Coder™.
Cosimulation with Cadence® Virtuoso® AMS Designer.
New ADC Examples
Learn how to evaluate and compare the performance of different ADCs
New PLL Examples
Learn how to design and analyze PLLs including phase noise
See release notes for details on any of these features and corresponding functions.
