Mixed-Signal Blockset
Design, analyze, and simulate analog and mixed-signal systems
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Mixed-Signal Blockset provides models of components and impairments, analysis tools, and test benches for designing and verifying mixed-signal integrated circuits (ICs).
You can model PLLs, data converters, and other systems at different levels of abstraction. These models can be used to simulate mixed-signal components together with complex DSP algorithms and control logic. You can customize models to include impairments such as noise, nonlinearity, jitter, and quantization effects. Rapid system-level simulation using variable-step Simulink solvers lets you debug the implementation and identify design flaws without simulating the IC at the transistor level.
With the Mixed-Signal Analyzer app you can analyze, identify trends in, and visualize mixed-signal data. The Cadence® Virtuoso ADE MATLAB Integration option lets you import databases of circuit-level simulation results into MATLAB. Alternatively, you can import a SPICE netlist and create or modify a linear, time-invariant circuit with parasitic elements extracted from the IC design. The blockset provides analysis functions for post-processing simulation results to verify specifications, fit characteristics, and report measurements.
Data Analysis and Optimization
Visualize, analyze, and identify trends in mixed-signal data, programmatically or interactively using the Mixed-Signal Analyzer app. The Cadence Virtuoso ADE MATLAB Integration option lets you import database simulation results and optimize your mixed-signal IC design from MATLAB.
Phase-Locked Loop Design
Design and simulate phase-locked loops (PLLs) at the system level. Typical architectures include integer-N PLLs with single or dual modulus prescalers and fractional-N PLLs with accumulators or delta-sigma modulators. Verify and visualize the open-loop and closed-loop responses of your designs.
ADC and DAC Design
Design and simulate analog-to-digital (ADC) and digital-to-analog (DAC) data converters at the system level. Typical architectures include delta-sigma modulators, flash, and successive approximation register (SAR) ADCs as well as binary weighted and segmented DACs.
Phase Noise and Jitter
Model clock and aperture jitter in ADCs and specify arbitrary phase noise profiles in the frequency domain for VCOs and PLLs. Perform eye measurements and jitter decomposition on arbitrary waveforms.
Measurements and Testbenches
Measure the lock time, phase noise profile, and operating frequency of PLLs. Characterize the performance of building blocks such as VCOs, PFDs, and charge pumps. Measure AC and DC characteristics and aperture jitter of ADCs.
Behavioral Models
Design your mixed-signal system using building blocks such as charge pumps, loop filters, phase frequency detectors (PFDs), voltage-controlled oscillators (VCOs), clock dividers, and sampling clock sources, among others. You can further refine analog models at a lower abstraction level with Simscape Electrical.
Product Resources:
“In the past, we didn’t know how well our designs would handle jitter until we tested them on the chip. Now that we run system-level simulations with discrete- and continuous-time models in Simulink, we have confidence that when we tape out a chip it’s going to work.”
Mixed-Signal Blockset FAQs
Mixed-Signal Blockset is a Simulink library that provides models of components and test benches for designing and verifying mixed-signal integrated circuits (ICs). You also find the Mixed-Signal Analyzer app and functions for analyzing data, visualizing trends, and creating reports.
You can design and simulate phase-locked loops (PLLs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal systems at different levels of abstraction.
You can customize models to include real-world impairments such as noise, nonlinearity, jitter, and quantization effects for accurate system-level simulation.
The Mixed-Signal Analyzer app is an interactive tool for visualizing, analyzing, and identifying trends in mixed-signal data. It directly integrates with Cadence to post-process simulation results, and to enable circuit optimization.
Yes, the Cadence Virtuoso ADE MATLAB Integration option lets you import databases of circuit-level simulation results into MATLAB. Additionally you can programmatically control Cadence simulation for IC design optimization.
Rapid system-level simulation using variable-step Simulink solvers lets you debug the implementation and identify design flaws without simulating the IC at the transistor level. Within Simulink you can directly integrate behavioral models of your IC together with control logic and digital signal processing algorithms.
The blockset includes PLL and Data Converter building blocks such as charge pumps, loop filters, phase frequency detectors (PFDs), voltage-controlled oscillators (VCOs), clock dividers, sampling clock sources, discrete and continuous Delta Sigma Modulators .
You can measure lock time, phase noise profile, and operating frequency of PLLs, as well as AC and DC characteristics and aperture jitter of ADCs. You can also inspect eye diagram metrics ad decompose jitter.
