FPGA Design with MATLAB, Part 5: Generating and Synthesizing RTL
From the series: FPGA Design with MATLAB
FPGA programming traditionally starts with providing register transfer level (RTL) VHDL® or Verilog® code to an FPGA synthesis tool. In this part of the tutorial we will show how to automatically generate RTL from the verified high-level architectural model, analyze estimated timing and resource usage, and then automatically run synthesis.
This video covers:
- Running checks for HDL code generation readiness and potential hardware inefficiencies
- Resolving the reported issues automatically or manually
- Setting up third-party tools to synthesize the generated VHDL or Verilog
- The stages, tasks, and settings for generating RTL code using the HDL Workflow Advisor
- Resource usage and optimization report, which provides fast high-level feedback before moving on to synthesis
- Analysis of the timing and critical path from FPGA synthesis
Welcome to the HDL Coder Video Series. In this video series we will learn a popular production proven path to take a MATLAB digital signal-processing algorithm through Simulink, Fixed-Point Designer, and HDL Coder to target an FPGA.
In previous videos in this series, we have discussed the strength of MATLAB and Simulink, created the Simulink model of the pulse detection algorithm, introduced design architecture options that extend control over speed and area tradeoffs, and converted the Simulink design to fixed point.
In part five of the video series we will generate and synthesize the optimized HDL code.
We will take the following steps to generate the HDL code. First, we will check the model’s compatibility for code generation and then launch the HDL Workflow Advisor to generate the HDL code.
The Pulse Detector subsystem or the device under test (DUT) contains the algorithm for which we will generate the HDL code. We will begin by saving and renaming the model and check for any incompatibility in the Pulse Detector subsystem. Select the “Check Model Compatibility” by right-clicking on the DUT under the HDL Code option. HDL Model Checker not only ensures if the blocks used in the subsystem are HDL compatible, but also ensures the settings, ports, and configurations of these blocks do not generate inefficient hardware.
The HDL model checker includes options for Native Floating Point and Industry Standard checks. As these are not applicable for this example, we shall ignore them. After the selected checks are run, noncompliant status is displayed as warnings or failures. In our case, two warnings are highlighted. To navigate to the source of the warning in the Simulink model, use the link provided. Reported warnings are likely to prevent optimization features to function properly and end up consuming additional hardware resources. To automatically correct the warnings, you can change them using the Modify settings.
A HTML report is generated, which shows results on each run of the Model Checker with a timestamp.
In the next step we will utilize the HDL Workflow Advisor to generate the HDL code. To synthesize the generated VHDL or Verilog Code, we will use a third-party tool; in our case, Xilinx Vivado. HDL Coder supports a broad range of synthesis tools such as Intel, Microsemi, to name a few. Using the “hdlsetuptoolpath” command, we will assign the synthesis tool to our MATLAB system path.
Launch the HDL Workflow Advisor by right-clicking the DUT, and select HDL Workflow advisor from the HDL Code option. The HDL Workflow Advisor guides you through the stages of generating HDL code for the DUT and the FPGA design stages using a range of tasks.
In order to run these tasks, we will set each of the task folder options with details of our design and hardware package. Information of the synthesis tool, target device details, and target frequency will be defined under the Set Target folder and settings relating to global reset and report generation are done in the HDL Code Generation Section.
Click APPLY to save the selected choices and right-click on sub-folder 3.2 and click ”RUN TO SELECTED TASK” to initiate generation of HDL code.
When HDL Advisor completes running the tasks, you have successfully generated the HDL code. The resulting generated HDL is well structured, commented, and readable, and you can navigate from specific lines of HDL code to the model or MATLAB code. The Code Generation report lets you review resource utilization estimates such as multiplier, DSP blocks, and optimization options such as pipelining, resource sharing, and delay balancing. Furthermore, you can view the model changes in the DUT using the Generated Model link option, and even simulate the generated model to ensure it works correctly with the optimized timing.
With the HDL code generated, you can either choose to utilize the Workflow Advisor to create the FPGA Synthesis project, else use a synthesis tool of your choice. In this video we will utilize the first option.
With the logic resources mapped on the FPGA, we can visualize and identify the pre- and post-routing timing information and highlight the critical paths in the model. This analysis uses the Annotate Model with Synthesis Result option and enables the HDL Coder to display the DUT with more accurate critical path timing. With the steps in the Workflow Advisor complete, you can verify the HDL by utilizing cosimulation on the Workflow Advisor. With the cosimulation option we can verify the RTL matches the Simulink and MATLAB behavior.
With this fifth and final video on the HDL Coder video series we have successfully generated and synthesized the optimized HDL Code for the Pulse Detection algorithm implemented in MATLAB.
To learn more on the HDL Coder product, visit the MathWorks website and explore MathWorks Getting Started page to design, explore, generate, and verify HDL code generation for FPGA, ASIC, or System on Chip (SoC) prototype or production projects.
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