Design Shift-Left: Enabling Early SerDes Mixed-Signal Design Beyond 200 Gb/s

High-speed mixed-signal systems, like 200+ Gb/s SerDes, integrate both analog and digital processing subsystems, resulting in complex interactions that can prolong design cycles and increase the likelihood of design issues. As manufacturing processes evolve and performance demands rise, these complexities intensify. Previous research demonstrated that validation efforts could be advanced in the workflow by using early architectural models to create behavioral mixed-signal simulation models. This paper extends that concept, showing that automatic model generation can also expedite circuit design by shifting some design work earlier in the process. By employing a SerDes system architectural model to create an analog-to-digital converter (ADC) behavioral model, the paper illustrates how ADC calibration schemes can be designed without a finalized ADC circuit. This approach allows for the parallel design and validation of calibration and ADC circuits, potentially reducing system design time by enabling simultaneous development of interacting subsystems.

This paper was presented at DesignCon 2022.