Meteorcomm Uses Simulink Testbench for Cycle-by-Cycle RTL Verification Using Multiple Cosimulation Blocks
“With the cosimulation model, one FPGA engineer finished three sets of stimulus checks in less than an hour. I spent one sprint (three weeks) to create the cosimulation testbench. Overall development time was reduced from nine to three weeks. The cosimulation bench can be reused to sync any changes, either from system models or from RTL.”
Key Outcomes
- Time saved and errors reduced by reusing the Simulink testbench in HDL cosimulation, which enabled verification of the HDL implementation without the need to handwrite SystemVerilog
- Results directly compared by synchronizing HDL design and reference models cycle by cycle in cosimulation
- Efficient debugging achieved within Simulink by using Logic Analyzer to view and compare signal values between system models and RTL cosim blocks
Testbench with HDL model, including a MATLAB model of a digital downconverter.
An expanded view of the digital downconverter RTL cosim blocks.
Meteorcomm supplies wireless communications and train control solutions to the railway industry. Recently, for a train communication system, the company needed to reuse as much as possible of a digital downconverter from a previous software-defined radio design for new product generation. Their design would take a radio-frequency signal and digitally tune it to move it to the baseband. From there, the signal would undergo several stages of filtering and preamble detection, with the recovered symbols transferred to a buffer in DDR memory for further processing by a processor.
Meteorcomm engineers started by developing a reference model for the design in Simulink® using a combination of MATLAB® functions and Simulink blocks. Then, their designers handwrote synthesizable HDL code to implement the design on a Zynq® UltraScale+™ MPSoC device. The conventional verification method would be to use the reference model to generate the input stimulus for the design under test (DUT), run simulations using a third-party HDL simulator, then verify the DUT by comparing outputs to the Simulink reference model.
This approach, however, is prone to error and can take several days to complete. To avoid these issues, Meteorcomm engineers chose to use the HDL cosimulation feature in HDL Verifier™. With HDL cosimulation, they could reuse the complete Simulink testbench, injecting the same stimulus into both the reference model and the DUT, and use result comparison blocks in Simulink to compare the two. To model the behavior of the RTL implementation more flexibly in Simulink, Meteorcomm engineers divided the system into modules and used a cosimulation block for RTL implementation of each module. Then they added delays between the cosimulation blocks to match the implementation difference between the RTL and Simulink.
With each stage having its own comparison block, applying identical stimuli to both models enabled Meteorcomm to match results cycle by cycle. Setting up new test runs with different stimuli only took minutes, significantly speeding up the process of verifying that the MATLAB model and HDL code behaved identically.
