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hdlcoder.FloatingPointTargetConfig class

Package: hdlcoder

Specify floating-point target configuration for floating-point library


The hdlcoder.FloatingPointTargetConfig object sets options for HDL Coder™ to generate synthesizable floating-point code. To create an hdlcoder.FloatingPointTargetConfig object for a floating-point library, use the hdlcoder.createFloatingPointTargetConfig function. You can create a floating-point configuration object for these floating-point libraries:

  • Native Floating Point

  • Altera® Megafunctions (ALTERA FP Functions)

  • Altera Megafunctions (ALTFP)

  • Xilinx® LogiCORE®


fpconfig = hdlcoder.createFloatingPointConfig(library) creates an hdlcoder.FloatingPointTargetConfig object for a floating-point library.

fpconfig = hdlcoder.createFloatingPointConfig(library,Name,Value) creates an hdlcoder.FloatingPointTargetConfig object that has additional options specified by one or more Name,Value arguments. Name can also be a property name and Value is the corresponding value. Name must appear inside single quotes (''). You can specify several name-value arguments in any order as Name1,Value1,...,NameN,ValueN.

The name-value arguments that you can specify depend on the library that you select for creating the floating-point configuration.

Input Arguments

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Floating-point library name, specified as a character vector.



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Native Floating Point

Specify whether you want HDL Coder to handle denormal numbers in your design. Specify this property as a character vector. Denormal numbers are nonzero numbers that are less than the smallest normal number.

Specify whether you want HDL Coder to use a maximum or a minimum latency setting for the floating-operators that your design uses. Specify this property as a character vector.

Specify how you want HDL Coder to implement the mantissa multiplication process for floating-point multipliers in your design. You can control the Digital Signal Processor (DSP) use on the target platform for your design. To learn more, see Mantissa Multiplier Strategy.

Altera FP Functions

Specify whether you want HDL Coder to initialize pipeline registers in the Altera Megafunction IP to zero. Specify this property as a logical. To avoid potential numeric mismatches in the HDL simulation, leave InitializeIPPipelinesToZero set to true.

ALTFP and Xilinx LogiCORE

Specify whether you want the design to map to a minimum or a maximum latency with Xilinx LogiCORE or Altera Megafunction IP. Specify this property as a character vector.

Specify whether you want to optimize the design for speed or area when mapping your design with Xilinx LogiCORE or Altera Megafunction IP. Specify this property as a character vector.


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This example shows how to create a floating-point target configuration with the native floating-point support in HDL Coder, and then generate code.

Create a Floating-Point Target Configuration

To create a floating-point configuration, use hdlcoder.createFloatingPointTargetConfig.

fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT')
fpconfig = 

  FloatingPointTargetConfig with properties:

            Library: 'NativeFloatingPoint'
    LibrarySettings: [1×1 fpconfig.NFPLatencyDrivenMode]
           IPConfig: [1×1 hdlcoder.FloatingPointTargetConfig.IPConfig]

Specify Custom Library Settings

Optionally, to customize the floating-point configuration, specify custom library settings.

fpconfig.LibrarySettings.HandleDenormals = 'off';
fpconfig.LibrarySettings.LatencyStrategy = 'MIN';
fpconfig.LibrarySettings.MantissaMultiplyStrategy = 'NoMultiplierFullAddShift';
ans = 

  NFPLatencyDrivenMode with properties:

             LatencyStrategy: 'MIN'
             HandleDenormals: 'off'
    MantissaMultiplyStrategy: 'NoMultiplierFullAddShift'
                     Version: '1.0.0'

View Latency of Native Floating Point Operators

The IPConfig object displays the maximum and minimum latency values of the floating-point operators.

ans = 

       Name              DataType            MaxLatency    MinLatency
    __________    _______________________    __________    __________

    'ABS'         'SINGLE'                    0             0        
    'ADDSUB'      'SINGLE'                   12             7        
    'ATAN'        'SINGLE'                   36            36        
    'ATAN2'       'SINGLE'                   42            42        
    'CONVERT'     'NUMERICTYPE_TO_SINGLE'     6             6        
    'CONVERT'     'SINGLE_TO_NUMERICTYPE'     6             6        
    'COS'         'SINGLE'                   27            27        
    'DIV'         'SINGLE'                   32            32        
    'EXP'         'SINGLE'                   23            23        
    'FIX'         'SINGLE'                    3             3        
    'LOG'         'SINGLE'                   20            20        
    'MINMAX'      'SINGLE'                    3             3        
    'MOD'         'SINGLE'                    0             0        
    'MUL'         'SINGLE'                    8             8        
    'POW2'        'SINGLE'                    2             2        
    'RECIP'       'SINGLE'                   19            19        
    'RELOP'       'SINGLE'                    3             3        
    'REM'         'SINGLE'                    0             0        
    'ROUNDING'    'SINGLE'                    5             5        
    'RSQRT'       'SINGLE'                   17            17        
    'SIGNUM'      'SINGLE'                    0             0        
    'SIN'         'SINGLE'                   27            27        
    'SINCOS'      'SINGLE'                   27            27        
    'SQRT'        'SINGLE'                   28            28        
    'UMINUS'      'SINGLE'                    0             0        

Generate Code

makehdl('sfir_single/symmetric_fir','FloatingPointTargetConfiguration',fpconfig, ...
### Generating HDL for 'sfir_single/symmetric_fir'.
### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 30 cycles.
### Output port 1: 30 cycles.
### Begin VHDL Code Generation for 'sfir_single'.
### Working on sfir_single/symmetric_fir/nfp_add_comp as C:\NativeFloatingPoint\hdlsrc\sfir_single\nfp_add_comp.vhd.
### Working on sfir_single/symmetric_fir/nfp_mul_comp as C:\NativeFloatingPoint\hdlsrc\sfir_single\nfp_mul_comp.vhd.
### Working on sfir_single/symmetric_fir as C:\NativeFloatingPoint\hdlsrc\sfir_single\symmetric_fir.vhd.
### Generating package file C:\NativeFloatingPoint\hdlsrc\sfir_single\symmetric_fir_pkg.vhd.
### Creating HDL Code Generation Check Report file://C:\NativeFloatingPoint\hdlsrc\sfir_single\symmetric_fir_report.html
### HDL check for 'sfir_single' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated VHDL code is saved in the hdlsrc folder.

Version History

Introduced in R2016b