HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. These are some of the key features:
Generation of target-independent HDL code that you can deploy on any FPGA or ASIC.
Support for the full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes.
Extensive support for math and trigonometric blocks.
Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.
|Create floating-point target configuration for floating-point library that you specify|
Overview of the native floating point support in HDL Coder and the various features supported.
How to generate HDL code from floating-point Simulink® models.
How you can verify the generated code from the floating-point model using HDL Testbench, Cosimulation, and FPGA-in-the-loop.
Numerical considerations when generating code with native floating-point and IEEE-754 compliance.
ULP considerations, ULP values of native floating-point operators, and adherence to IEEE-754 compliance.
Learn how to view the latency of a floating point operator and the various ways to customize it.
List of operators and supported blocks in the floating-point model.
Latency values of operations supported in native floating-point mode.
Find the estimated critical paths in your design without using third-party synthesis tools.
HDL code generation parameters supported for specific block implementations in Native Floating Point.
Causes and possible solutions for fixing error message related to delay allocation issue for floating-point operations.
Causes and possible solutions for fixing HDL code generation issues with multirate models that have large rate differentials.