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ASIC Testbench

Generate testbenches for ASIC and advanced FPGA designs

ASIC Testbench for HDL Verifier™ is an add-on that enables HDL Verifier to generate test components and verification models from MATLAB® or Simulink® into Universal Verification Methodology (UVM) or SystemVerilog environments. These models run natively in your HDL simulator.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on.