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Phase-Locked Loops

Design and simulate analog phase-locked loop (PLL) systems

Design a PLL system starting from basic foundation blocks or from a family of reference architectures. Simulate and analyze the PLL system to verify key performance metrics until you meet the system specifications.

You can start by providing the specifications and impairments of each foundation block and connect the blocks to model different PLL architectural models (bottom-up approach). Alternatively, you can start from complete system-level models of typical PLL architectures and customize those models to meet your system specifications (top-down approach).

Use Measurements and Testbenches throughout the design process to verify the specifications of the blocks and of the entire system in presence of imperfections.

Blocks

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Charge PumpOutput a current proportional to the difference in duty cycle between two input ports (Since R2019a)
Loop FilterModel second-, third-, or fourth-order passive loop filter (Since R2019a)
PFDPhase/frequency detector that compares phase and frequency between two signals (Since R2019a)
VCOModel voltage controlled oscillator (Since R2019a)
Ring Oscillator VCOModel ring oscillator VCO (Since R2021a)
Single Modulus PrescalerInteger clock divider that divides frequency of input signal (Since R2019a)
Dual Modulus PrescalerInteger clock divider with two divider ratios (Since R2019a)
Fractional Clock Divider with AccumulatorClock divider that divides frequency of input signal by fractional number (Since R2019a)
Fractional Clock Divider with DSMDelta Sigma Modulator based fractional clock divider (Since R2019a)
Fractional N PLL with AccumulatorFrequency synthesizer with accumulator based fractional N PLL architecture (Since R2019a)
Fractional N PLL with Delta Sigma ModulatorFrequency synthesizer with delta sigma modulator based fractional N PLL architecture (Since R2019a)
Integer N PLL with Dual Modulus PrescalerFrequency synthesizer with dual modulus prescaler based integer N PLL architecture (Since R2019a)
Integer N PLL with Single Modulus PrescalerFrequency synthesizer with single modulus prescaler based integer N PLL architecture (Since R2019a)

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