Simulink® Design Verifier™ uses formal methods to identify hidden design errors in models. It detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. It can formally verify that the design meets functional requirements. For each design error or requirements violation, it generates a simulation test case for debugging.
Simulink Design Verifier generates test cases for model coverage and custom objectives to extend existing requirements-based test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives. In addition to coverage objectives, you can specify custom test objectives to automatically generate requirements-based test cases.
Overview of features and capabilities of Simulink Design Verifier to help you get started with formal verification.
Identify hidden design errors in your model by using design error detection analysis.
Analyze a simple control system model that demonstrates Simulink Design Verifier capabilities.
Overview of the basic Simulink Design Verifier workflow.
Recorded Webinar: Formal Verification Made Easy with MATLAB and Simulink
Introduction to formal verification with Simulink Design Verifier.
What Is Simulink
Introduction to Simulink Design Verifier.