Problem in generating reusable Verilog code using Simulink HDL Coder
3 views (last 30 days)
Show older comments
I am trying to generate a reusable Verilog code for an atomic Masked subsystem using Simulink HDL Coder . In my midel there are two such subsystems used. Both the subsystem is same except there mask parameter value. But while generating Verilog Code, it is generating one file for each subsytem.
Both the subsytem is linked to a library (User defined) block.
The DefaultParameterBehavior Configuration Parameter is set to Inlined. The mask parameters are non tunable. The Generate parameterized HDL code from masked subsystem option is enabled.
I am sharing the generated Verilog code of the top module that instantiates both the subsystem blocks.
I need that it will generate only one file (constant1.v) instead of two and instatntitaed using only constant1.
constant1 #(.a(0),
.b(0),
.c(0),
.d(1)
)
u_constant1 (.Out1(constant1_out1), // uint32
.Out2(constant1_out2), // uint32
.Out3(constant1_out3), // uint32
.Out4(constant1_out4) // uint32
);
constant2 #(.a(0),
.b(0),
.c(1),
.d(2)
)
u_constant2 (.Out1(constant2_out1), // uint32
.Out2(constant2_out2), // uint32
.Out3(constant2_out3), // uint32
.Out4(constant2_out4) // uint32
);
0 Comments
Answers (1)
Kiran Kintali
on 31 Jul 2022
Feel free to reach out to technical support for this question.
You may want to try to use the new subsystem reuse algorithm available with HDL Coder https://www.mathworks.com/help/hdlcoder/ug/generating-reusable-code-for-atomic-subsystems.html
hdlset_param('myHDLModel', 'SubsystemReuse', 'Atomic and Virtual')
See Also
Categories
Find more on Ports and Subsystems in Help Center and File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!