Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor

Hi, I have a generator controller model in Simulink, I'm hoping to have it deployed on Speedgoat (IO334-325k) and use it to run a real generator. I have five analog input channels and one TTL discrete output channel.

My first question is, am i correct in understanding that the FPGA sample frequency is how fast the FPGA internal signals are sampled? (for example, if i have a discrete transfer function in my model, is it seeing the 'FPGA sample frequency' as the sample rate? This is important because discrete transfer functions only work properly at the correct sample rate).

Second question, I read from here (Troubleshooting Real-Time Hardware Deployment Issues in Simscape Hardware-in-the-Loop Workflow - MATLAB & Simulink - MathWorks France) that FPGA sample frequency = FPGA clock frequency/(Oversampling factor x Number of solver iterations), also from here (hdl coder oversampling factor - Google Search) that Oversampling factor = FPGA clock frequency/ Simulink solver rate. Does it mean if the number of solver iterations is 1, then FPGA sample frequency equals the simulink solver rate? I also don't understand why the simulink solver rate is part of the equation provided that my model only has analog and discrete IOs from/to the outside world, or does it mean in my case, the Oversampling factor = FPGA clock frequency/ ADC rate?

I would really appreciate it if you could help me with the questions above, Thank you very much in advance.

Yeung

Answer 1

[Kiran Kintali]

Simscape to HDL workflow

if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit. I will try to find relevant doc links as well.

This page describes the same Troubleshooting Real-Time Hardware Deployment Issues in Simscape Hardware-in-the-Loop Workflow - MATLAB & Simulink (mathworks.com) and

this page is for troubleshooting validation errors Troubleshoot Validation Errors in Simscape Hardware-in-the-Loop Workflow - MATLAB & Simulink (mathworks.com)

Simulink to HDL workflow

If your model is a pure controller running on speedgoat FPGA hardware, the following page has additional notes on this topic.

https://www.mathworks.com/matlabcentral/answers/2130011-fixing-clock-frequency-and-sample-time-of-control-system-model-using-hdl-coder

If you can share your model we can give specific guidance. Thanks.

[Yeung Pok Nga]

Many thanks for your reply.

I read HDL Coder Evaluation Reference Guide R2023b.pdf you attached under the other post but i couldn't find any section that explains the relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor.

Section 2.1.1 states that 'For a single-rate model, 1 time step in Simulink maps to 1 clock cycle in HDL.', and it also says 'If you model your sample time to be equal to the actual clock speed, that does not mean it will achieve this clock speed during RTL synthesis and implementation.' but it doesn't elaborate any further. In my case, the simulink sample time is 10microsecond, if that's mapped to clock cycles that would mean a clock speed of 100k Hz, but the range of my fpga clock speed is 50M to 250MHz, how does the HDL coder map that?

Looking forward to your reply