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EDA Simulator link and Simulink Cosimulation

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Hello All,
I am trying to use EDA simulator link with simulink but I am getting the error:
Error reported by S-function 'shdlcosim' in 'fpgs_sim/HDL Cosimulation/S-Function':
Continuous sample time not allowed for input port 1 of cosim block.
Now what am I supposed to do? The input is actually fixed point 12 bit signed but still I get the error. I have attached the simulink file. Please help....

Accepted Answer

Tim McBrayer
Tim McBrayer on 13 Feb 2012
The rate to choose is your design decision. Somewhere in your design I suspect that you have a source (or multiple sources) running at a continuous rate. Turn on Sample Time coloring to see what rates are where; blocks and signals running at continuous rate show up as black. The EDA Simulator Link block requires a discrete rate on all its inputs, as a HDL simulator is a discrete event simulator. It's possible that all you have to do is to choose a fixed-step discrete solver for your model.

More Answers (2)

Tim McBrayer
Tim McBrayer on 13 Feb 2012
The error message is referring to the signal's rate, not its data type. You will need to change the rate of the Simulink signal(s) feeding into the EDA Simulator Link block so that they have a discrete rate. (A continuous signal has a rate of 0; a discrete signal has a rate > 0.) Two ways to do this are to ensure all your sources have a discrete rate, or to add rate transition blocks immediately before the signals feed into the Link block.
  1 Comment
shreyas on 13 Feb 2012
So what data rate should I use? The error is coming on a port which has one end at EDA simulator which expects 14 bits of fixed point data and the the other end is from a Convert block which is connected to a A/D measurement. The sample time of the convert block is -1. Now what should I keep the sample time of the rate transition and the convert block?? I dont know how to attach the simulink file here? Can I send it to your email:

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Sean Little
Sean Little on 13 Feb 2012
What clock rate do you want to simulate in your HDL? That is what determines the sample rate in Simulink. It sounds like you should spend some time reading the documentation for both Simulink and the EDA Link.

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