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Fpga-in-the-loop using IP core generation workflow with reference design?

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I would like to generate a baseband processor IP using HDL coder and implement it on an FPGA connected to Simulink (in the loop). The goal is to allow easy configuration of IP parameters and inspection of performance metrics. One particular constraint is that the design within the FPGA has many other components, so at first my understanding is that I should adopt the "IP Core Generation" workflow within the HDL Coder Workflow advisor and adapt the current FPGA design with "blank" connections for the IP that I intend to generate, then use this design as a reference design. However, from what I read, I understood that the FPGA-in-the-loop functionality is only enabled for the "Generic ASIC/FPGA" or the "FPGA Turnkey" workflows, both which do not allow a reference design to be included.
Have I misunderstood it? What would be an advisable solution in this case, to allow Simulink connectivity to the FPGA and also integrate an IP generated by HDL coder with a reference design?

Accepted Answer

Tao Jia
Tao Jia on 5 May 2017
Hi Igor,
Currently the IP core generation workflow does not support FPGA-in-the-Loop.
If you want to communicate with the generated IP core on FPGA from MATLAB/Simulink, you can check out this one and see if it helps:

More Answers (1)

Igor Freire
Igor Freire on 5 May 2017
Thanks for the information. These alternatives may be helpful at some point. However, I think the use that I was envisioning in fact would require the FPGA-in-the-loop functionality. Anyways, your answer solves my question.

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