photo

Igor Freire


Universidade Federal do Pará

Last seen: 7 months ago Active since 2017

Followers: 0   Following: 0

Message

Statistics

MATLAB Answers

1 Question
1 Answer

RANK
294,818
of 298,615

REPUTATION
0

CONTRIBUTIONS
1 Question
1 Answer

ANSWER ACCEPTANCE
100.0%

VOTES RECEIVED
0

RANK
 of 20,624

REPUTATION
N/A

AVERAGE RATING
0.00

CONTRIBUTIONS
0 Files

DOWNLOADS
0

ALL TIME DOWNLOADS
0

RANK

of 161,826

CONTRIBUTIONS
0 Problems
0 Solutions

SCORE
0

NUMBER OF BADGES
0

CONTRIBUTIONS
0 Posts

CONTRIBUTIONS
0 Public Channels

AVERAGE RATING

CONTRIBUTIONS
0 Highlights

AVERAGE NO. OF LIKES

  • Thankful Level 1

View badges

Feeds

View by

Answered
Fpga-in-the-loop using IP core generation workflow with reference design?
Hi, Thanks for the information. These alternatives may be helpful at some point. However, I think the use that I was envision...

8 years ago | 0

Question


Fpga-in-the-loop using IP core generation workflow with reference design?
Hi, I would like to generate a baseband processor IP using HDL coder and implement it on an FPGA connected to Simulink (in th...

8 years ago | 2 answers | 0

2

answers