filWizard: Error during Validation of Altera Stratix IV GX 230 FPGA development kit
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THOUMY François on 27 Apr 2017
Commented: Mohamed BAGHDADI on 17 May 2021
I'm trying to use filWizard to connect Matlab to a Altera Stratix IV GX 230 FPGA development kit board via Ethernet.
When I run the FPGA-in-the-loop-test to validate the connection, I get the following messages:
Starting FPGA-in-the-Loop test ...
Generating FPGA programming file ...Passed
Programming FPGA ...Passed
Checking Ethernet connection ...Passed
Running FIL simulation ...Failed
Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
My configuration is the following:
Matlab R2017A with HDL Verifier toolbox
PC IP config 192.168.0.2
Board address 192.168.0.1
PC and board connected through a crossed cable (I also tried with a switch).
I'm using a Quartus licence given with the Altera development kit, then the IP core related to Ethernet is time limited (Info (115017): Design contains a time-limited core -- only a single, time-limited programming file can be generated).
Could it be the cause of the issue ?
Thanks for any help
Tao Jia on 28 Apr 2017
I think your guess might be correct. We do use the Altera Etherent SGMII to GMII IP in your setup. It requires an additional Altera license to work properly.
You can try to use Altera Quartus programmer to program FPGA with the auto generated sof file. It will have a command-line window opened at the end. You'll need to make it remain open to make the FPGA to continue working.
Another option is to try the JTAG interface which does not require any licensed Altera IP.
Hope this helps, Tao
Hoan Tran on 4 Oct 2017
Edited: Hoan Tran on 4 Oct 2017
Hi, Im getting the same problem, although I passed the FPGA-in-the-loop validation and loading bitstream successfully to development kit, I get the following error when I run FIL Simulink model.
"did not receive version information from the hardware. you must have a valid connection, a compatible development board, and compatible versions of the block and fpga programming file"
My configuration is:
Quartus Prime 16.0 Standard and also try Quartus 13sp1/
Altera Stratix IV GX 230 FPGA/
Thanks for your help
Mohamed BAGHDADI on 17 May 2021
Hey, Did you solve it? I am experimenting the same.
PS: I am using Matlab 2019b, altera cyclone IV GX and Quartus prime 18.1.
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