How can I modify mapping options in HDL Workflow Advisor in Simulink?

Hi everyone.

I am trying to implement a design on a FPGA using Simulink's HDL Workflow Advisor. The block that I am trying to implement is giving errors after step 4.2.2 under "perform mapping". I took the VHDL code that was generated and inserted it on Xilinx. In Xilinx, activating some options like "area optimization" makes the implementation possible. The thing is, Matlab can call Xilinx to implement the design, but it does so with the default options, and I cannot activate the flag "-global_opt area" that makes the implementation possible. There is no such option in Simulink, and I cannot find where I can modify the command that Simulink sends to Xilinx to perform the mapping.

Does anyone have any idea? I can provide more details or screenshots if needed.

Thank you.

Answer 1

[Kiran Kintali]

After code generation HDLCoder creates a Vivado Project and configures the project with generated files. You should see a link to open vivado project solution. See the hyperlink in the image below. Clicking on the link opens up the vivado project. You should be able to set options in the project and continue with rest of the steps in workflow advisor.

You can also export the manually set options as .tcl file from vivado and attach them as "additional project creation tcl files" as shown in the option below for future runs.