I'm working on an SoC design that involves a single memory channel only (for I/O reasons) and storing four parallely processed image frames in that channel using an offset. For data coherency, I'm trying to implement different clock rates inside of the PL using rate transistion blocks. This is all nested in a subsystem called "FPGA". I'm getting this error when trying to do so though:
I've attached the Simulink model too. Thanks!