GN Hearing Accelerates Development of Next-Generation Hearing Aid ASICs
Accelerate the development of next-generation hearing aid ASICs
Use Simulink and Mixed-Signal Blockset to model and simulate magnetic induction radio communications in the presence of noise, clock jitter, and other impairments
- Design time shortened by months
- Costly ASIC prototypes minimized
- Power consumption reduced
Advanced hearing aid technology requires communication between a pair of devices, one located in or behind each ear. This communication channel serves multiple objectives, including synchronizing the devices, transmitting audio from one device to another, and detecting the direction of the sound source. To achieve these objectives, the signal must be transmitted with minimal delay and power usage to preserve battery life.
GN Hearing has developed next-generation hearing aids that use magnetic induction radios to enable low-latency, low-power communication between devices. Engineers created a system-level Simulink® model of their design, which they used to verify the design’s performance in the presence of noise, clock jitter, and other impairments before implementing on an ASIC.
“In the past, we had to wait until we got the first chip before we could see if we had a problem with clock jitter,” says Henrik Holm Johansen, an audio specialist at GN Hearing. “Now we run simulations in Simulink to analyze jitter and check the design before we tape out the chip, so we need fewer prototypes. This is a big advantage for us because each additional prototype adds significant costs and six months or more to the schedule.”
Each magnetic induction radio in the company’s hearing aids has its own clock. In the past, engineers would create a single model with one ideal clock source when designing transmitters and receivers. While such a model enabled the team to validate the functionality of their design, it did not accurately reflect its real-world application with independent, asynchronous clocks in both devices.
The team wanted to model separate clocks as well as clock skew, jitter, and noise. This would enable them to evaluate and properly size the phase-locked loops (PLL) in the receiver. Without accurate simulations, the team risked under-designing the PLL, which could lead to bit errors. The lack of accurate simulations could also lead to over-designing the PLL, which would result in unnecessary costs and decreased battery life.
Working in Simulink, GN Hearing engineers created a system-level model of the magnetic induction radio transmitter and receiver that included continuous- and discrete-time signals.
They used blocks from Communications Toolbox™ to implement digital modulation and carrier synchronization and blocks from Mixed-Signal Blockset™ to model the analog PLL system in the receiver.
To generate clock signals with aperture jitter impairments, the team started with a Sampling Clock Source block and then added a Variable Pulse Delay block to increase the jitter.
The engineers then ran simulations in which they varied the amount of jitter, clock skew, and channel noise and measured the bit error rate to verify the design.
They also generated eye diagrams to see how noise affected system performance as well as constellation diagrams to visualize the constellation of the modulated signal.
The team later developed a set of test scripts in MATLAB® that automated the process of varying jitter, skew, and noise. They used these tests scripts to verify changes to the design as they continued to refine it.
Once the engineers had a design that worked well across the range of expected operating conditions, they provided key parameter values for the PLL and other results to the analog design team, who used these values to complete the ASIC design.
GN Hearing is now extending the use of Simulink to the analysis, design, and verification of mixed-signal audio components for the company’s hearing aids.
- Design time shortened by months. “Simulating our design in Simulink saved us three months or more in design time,” says Holm Johansen. “Without Simulink, our PLL team would have to spend a much longer time running circuit-level simulations, or we would have had to rely on our gut feelings for the initial PLL design.”
- Costly ASIC prototypes minimized. “Because prototypes are so costly, our goal is to limit them to a single, multiproject wafer and then a single, full mask chip,” says Holm Johansen. “Validating our design in Simulink, before any prototype is produced, has enabled us to achieve this goal and save the hundreds of thousands of dollars and months of delays that come with each additional prototype.”
- Power consumption reduced. “Evaluating design trade-offs with system-level simulations in Simulink enabled us to design an optimal PLL, instead of one that was larger and more complex than necessary,” notes Johansen. “As a result, we reduced power consumption and extended battery life.”