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Run and Verify IP Core

Prototype, simulate, and verify the generated IP core on your target FPGA device

Run and verify the generated bitstream from your IP core design on your target hardware. The input is a generated bitstream for the FPGA portion of your device. The output is a simulated and verified design running on your target FPGA. For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.

Run and Verify IP Core on Target Hardware Workflow


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fpgaAccess target FPGA or SoC device from MATLAB
hdlcoder.DUTPortDUT port from an HDL Coder generated IP core, saved as an object array
xilinxsocConnection to processor on Xilinx SoC board
intelsocConnection to processor on Intel SoC board


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addAXI4SlaveInterfaceWrite data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
addAXI4StreamInterfaceWrite data to IP core or read data from IP core using AXI4-Stream interface
mapPortMaps a DUT port to specified AXI4 interface in HDL IP core
writePortWrite data to a DUT port from MATLAB
readPortReads output data and returns it with the port data type and dimension
releaseRelease the hardware resources associated with the fpga object
systemRun command in Linux shell on SoC board
getFileTransfer file from SoC board to host computer
putFileTransfer file from host computer to SoC board
deleteFileDelete file on SoC board
dirList directory contents on SoC board
programFPGAProgram FPGA and set corresponding device tree from processor on SoC board