Chart

Implement control logic with finite state machine

Libraries:
Stateflow

Description

The Chart block is a graphical representation of a finite state machine based on a state transition diagram. In a Stateflow^® chart, states and transitions form the basic building blocks of a sequential logic system. States correspond to operating modes and transitions represent pathways between states. For more information, see Model Finite State Machines by Using Stateflow Charts.

To implement control logic, Stateflow charts can use MATLAB^® or C as the action language. For more information, see Differences Between MATLAB and C as Action Language Syntax.

Chart properties specify how your Stateflow chart interfaces with the Simulink^® model. You can modify chart properties in the Property Inspector, the Model Explorer, or the Chart properties dialog box. For more information, see Specify Properties for Stateflow Charts. Alternatively, you can modify chart properties programmatically by using Stateflow.Chart objects. For more information about the Stateflow programmatic interface, see Overview of the Stateflow API.

Examples

Design a Game by Using Stateflow

Implement the game of Tetris by using a Stateflow® chart. This model is a redesigned version of the classic Stateflow demo sf_tetris. The new design incorporates these programming paradigms:

Open Model

Model an Elevator System by Using Atomic Subcharts

Model a two-car elevator system by using linked atomic subcharts in Stateflow®. The elevator system consists of a Simulink® model and a user interface (UI). The model contains two Stateflow charts:

Open Model

Model a Fitness Tracker

Implement a fitness tracker by using temporal logic and messages.

Open Model

Ports

Input

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Port_1 — Input port
scalar | vector | matrix

When you create input data in the Symbols pane, Stateflow creates input ports. The input data that you create has a corresponding input port that appears once you create data.

Output

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Port_1 — Output port
scalar | vector | matrix

When you create output data in the Symbols pane, Stateflow creates output ports. The output data that you create has a corresponding output port that appears once you create data.

Parameters

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Parameters on the Code Generation tab require Simulink Coder™ or Embedded Coder^®.

Main

Show port labels — Select how to display port labels
`FromPortIcon` (default) | `none` | `FromPortBlockName` | `SignalName`

Select how to display port labels on the Chart block icon.

none: Do not display port labels.
FromPortIcon: If the corresponding port icon displays a signal name, display the signal name on the Chart block. Otherwise, display the port block name.
FromPortBlockName: Display the name of the corresponding port block on the Chart block.
SignalName: If a signal name exists, display the name of the signal connected to the port on the Chart block. Otherwise, display the name of the corresponding port block.

Programmatic Use

Parameter: ShowPortLabels

Type: string scalar or character vector

Value: "none""FromPortIcon" | "FromPortBlockName" | "SignalName"

Default: "FromPortIcon"

Read/Write permissions — Select access to contents of chart
`ReadWrite` (default) | `ReadOnly` | `NoReadOrWrite`

Control user access to the contents of the chart.

ReadWrite: Enable opening and modification of chart contents.
ReadOnly: Enable opening but not modification of the chart. If the chart resides in a block library, you can create and open links to the chart and can make and modify local copies of the chart but you cannot change the permissions or modify the contents of the original library instance.
NoReadOrWrite: Disable opening or modification of chart. If the chart resides in a library, you can create links to the chart in a model but you cannot open, modify, change permissions, or create local copies of the chart.

Programmatic Use

Parameter: Permissions

Type: string scalar or character vector

Value: "ReadWrite" | "ReadOnly" | "NoReadOrWrite"

Default: "ReadWrite"

Minimize algebraic loop occurrences — Control elimination of algebraic loops
off (default) | on

off: Do not try to eliminate any artificial algebraic loops that include the atomic subchart.
on: Try to eliminate any artificial algebraic loops that include the atomic subchart.

Programmatic Use

Parameter: MinAlgLoopOccurrences

Type: string scalar or character vector

Value: "off" | "on"

Default: "off"

Sample time — Specify time interval
`-1` (default) | `Ts` | `0`

Specify the sample time of the Stateflow chart. Using Sample time to set the sample time for your Stateflow chart is not recommended. Instead, set the sample time through the Stateflow chart properties. See Stateflow Chart Properties for more information.

-1: Specify inherited sample time.
Ts: Specify discrete sample time.
0: Specify continuous sample time.

Programmatic Use

Parameter: SystemSampleTime

Type: string scalar or character vector

Value: "-1" | "[Ts 0]"

Default: "-1"

Code Generation

Function packaging — Select code format
`Auto` (default) | `Inline` | `Nonreusable function` | `Reusable function`

Select the generated code format for an atomic (nonvirtual) subchart.

Auto

Simulink Coder chooses the optimal format for your system based on the type and number of instances of the chart that exist in the model.

Inline

Simulink Coder inlines the chart unconditionally.

Nonreusable function

Simulink Coder explicitly generates a separate function in a separate file. Charts with this setting generate functions that might have arguments depending on the Function interface (Simulink) parameter setting. You can name the generated function and file using parameters Function name (Simulink) and File name (no extension) (Simulink) respectively. These functions are not reentrant.

Reusable function

Simulink Coder generates a function with arguments that allows reuse of chart code when a model includes multiple instances of the chart.

This option generates a function with arguments that allows chart code to be reused in the generated code of a model reference hierarchy that includes multiple instances of a chart across referenced models. In this case, the chart must be in a library.

Tips

When you want multiple instances of a chart represented as one reusable function, you can designate each one of them as Auto or as Reusable function. It is best to use one because using both creates two reusable functions, one for each designation. The outcomes of these choices differ only when reuse is not possible. Selecting Auto does not allow for control of the function or file name for the chart code.
The Reusable function and Auto options both determine whether multiple instances of a chart exist and the code can be reused. The options behave differently when it is impossible to reuse the code. In this case, Auto yields inlined code, or if circumstances prohibit inlining, separate functions for each chart instance.
If you select the Reusable function while your generated code is under source control, set File name options to Use subsystem name, Use function name, or User specified. Otherwise, the names of your code files change whenever you modify your model, which prevents source control on your files.

Dependency

This parameter requires Simulink Coder.
Setting this parameter to Nonreusable function or Reusable function enables the following parameters:
- Function name options
- File name options
- Memory section for initialize/terminate functions (requires Embedded Coder and an ERT-based system target file)
- Memory section for execution functions (requires Embedded Coder and an ERT-based system target file)
Setting this parameter to Nonreusable function enables Function with separate data (requires a license for Embedded Coder and an ERT-based system target file).

Programmatic Use

Parameter: RTWSystemCode

Type: string scalar or character vector

Value: "Auto" | "Inline" | "Nonreusable function" | "Reusable function"

Default: "Auto"

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

Active State Output

To generate an output port in the HDL code that shows the active state, in the Properties window of the chart, select Create output for monitoring. The output is an enumerated data type. See Simplify Stateflow Charts by Incorporating Active State Output.

Registered Output

To insert an output register that delays the chart output by a simulation cycle, use the OutputPipeline (HDL Coder) block property.

HDL Block Properties

ClockDrivenOutput	Enable clock-driven outputs to prevent combinatorial logic from driving the output and to allow an immediate output update when the clock signal and state change. The default is `off`. When you set ClockDrivenOutput to `on`, HDL Coder adds an output register that updates when the state updates. The final output variable is then assigned a value from the clock-drive register. This option is available only for Moore charts.
ConstMultiplierOptimization	Canonical signed digit (CSD) or factored CSD optimization. The default is `none`. See also ConstMultiplierOptimization (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is `inherit`. See also DistributedPipelining (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
InstantiateFunctions	Generate a VHDL^® `entity` or Verilog^® `module` for each function. The default is `off`. See also InstantiateFunctions (HDL Coder).
LoopOptimization	Unroll, stream, or do not optimize loops. The default is `none`. See also LoopOptimization (HDL Coder).
MapPersistentVarsToRAM	Map persistent arrays to RAM. The default is `off`. See also MapPersistentVarsToRAM (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
ResetType	Suppress reset logic generation. The default is `default`, which generates reset logic. See also ResetType (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
VariablesToPipeline	Warning `VariablesToPipeline` is not recommended. Use `coder.hdl.pipeline` (HDL Coder) instead. Insert a pipeline register at the output of the specified MATLAB variable or variables. Specify the list of variables as a character vector, with spaces separating the variables.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

To learn about restrictions of using charts, see Introduction to Stateflow HDL Code Generation (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

PLC Block properties

UseExternalDefinition

Suppress block definition in generated code. The default is Off. See also UseExternalDefinition (Simulink PLC Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

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R2023b: Convert to Chart

To convert to a state transition table, use the object function convertToSTT.

Chart

Description