How to do FPGA-in-the-loop simulation with Altera DE2-115 board?

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I successfully created a FIL block out of my VHDL code using filWizard. It was also possible to load the bitfile to the board (DE2-115).
Trying to simulate the design, I get the following error message: Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
Pinging the board is not successfull. DE2-115 board is connected to the computer via an 1Gbs switch where also the company's network is conneted to. DE2-115 was configured having an IP from the same subnet as the computer.
What could be the Problem? Do I have to do some DE2-115 specific settings (e.g. JP1 position, MAC address, ...)?
Mohamed BAGHDADI on 17 May 2021
Hey, Did you solve it? I am experimenting the same.
PS: I am using Matlab 2019b, altera cyclone IV GX and Quartus prime 18.1.
thank you

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Answers (1)

Tao Jia
Tao Jia on 30 Oct 2013
The switch is the problem. In HDL Verifier documentation, it says that the FPGA board must be connected to the host computer directly, i.e., a point to point connection.

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