IDT-Newave Reduces Semiconductor Design Time by Months

To reduce development time and meet project deadlines, IDT-Newave sought to improve their design process and increase collaboration between system and circuit designers.

Previously, they quantized their digital filters manually and verified their register transfer-level (RTL) implementation in Verilog^®, a time-consuming process.

“We spent a lot of time getting the filter response to fit, extending the word length, and obtaining the frequency response,” explains Liu. “We needed to redesign and convert the digital filter coefficients or quantize the digital filters again and again.”

IDT-Newave also needed to detect algorithm faults and system design flaws before implementation.

“We have to analyze many different phase noise sources,” says Liu. “This task is vital to successful design.”

IDT-Newave used MathWorks tools to revamp their design process and develop a variety of semiconductors, including a voiceband CODEC, a line equalizer, and a phase-locked loop (PLL) system. Some of the largest telecommunications equipment manufacturers in China, including ZTE, use these semiconductors today.

Designing Voiceband CODECs

Using MathWorks tools, IDT-Newave designed a voiceband CODEC chip that minimizes noise by converting analog signals from 4 kHz to a 14-bit/8 kHz sample signal, and converting digital voiceband signals to analog signals.

Engineers used MATLAB^® and DSP System Toolbox™ to design analog and digital filters for decimation, interpolation, bandpass, lowpass, and upsampling. Using DSP System Toolbox, IDT-Newave also determined the oversampling ratio and signal modulator order.

They then used Simulink^® to build a complete system-level model that served as a test harness for the behavioral model of the hardware and the DSP implementation.

IDT-Newave ran floating-point and fixedpoint simulations to verify system performance using Simulink, Fixed-Point Designer™, and DSP System Toolbox.

They then used Fixed-Point Designer to determine the optimal data path width and filter coefficient sizes and to verify the quantization effects in designing a DSP core with minimum size and power dissipation. The DSP was programmed in assembly code and validated with the Simulink model.

Engineers used the test harness to verify the behavioral model and the RTL implementation.

“MathWorks tools let us quantize the filter responses and coefficients and analyze the filter response within an integrated environment,” explains Liu. “Now all the parameters can be optimized before running the time-consuming RTL simulations.”

They used MATLAB Compiler™ to compile a graphical user interface that helps customers select optimal filter coefficients. MATLAB Compiler also enabled IDT-Newave to provide internal design teams with jitter analysis algorithms and data analysis utilities.

Identifying Fatal Design Flaws in a Line Equalizer

MathWorks tools helped IDT-Newave identify potentially fatal design errors and flaws in the line equalizer’s tuning algorithm before implementation.

Using Simulink, engineers designed an optimal line equalizer architecture and determined that the analog circuit design had too much noise. The system designers worked with the circuit designers to reduce the noise by ensuring an appropriate equalizer gain.

They modeled the line equalizer and cable using MATLAB, DSP System Toolbox, and Communications Toolbox™.

Using a combination of Simulink and Verilog, IDT-Newave analyzed mixed-signal simulations and implemented the prototype algorithm. They converted the Verilog model into a Simulink model using S-functions and identified the algorithm flaw as a finite state machine error.

“The circuit design and verification teams were stuck, and couldn’t find a solution to the problem,” explains Liu. “MathWorks tools played a decisive role in identifying fatal tuning logic errors by providing an interactive simulation environment that enabled us to easily change simulation conditions and log data. This greatly aided the debugging process.”

IDT-Newave designed an entire family of line equalizer products that are successfully selling today. They are using MathWorks tools to improve the design of future versions of the product.

Analyzing a PLL System

With MATLAB and Simulink, IDT-Newave designed digital signals for SONET/SDH systems and mixed-signal PLLs for PC clocks between 40 and 100 picoseconds of jitter.

“In just one month, our system-level engineers and circuit designers determined optimal jitter performance with PLLs designed with MathWorks tools,” says Liu.

They used MATLAB and Control System Toolbox™ to design the PLL system model. They ported the model to Simulink to run system simulations.

Using MATLAB and Control System Toolbox, system designers analyzed the interaction between the loop and phase margins to ensure stability under adverse conditions and power, voltage, and temperature variations.

They worked with circuit designers to run behavioral simulations and determine the impact of power loss noises in the circuit-level model.

“Before, running circuit-level simulations to identify the impact of the phase noise took four days,” explains Liu. “Using a unified PLL design and analysis approach with MathWorks tools enabled us to reduce that time to a half day or even less.”

They designed and implemented the PLL tuning and filtering algorithms with MATLAB and Simulink.

“MATLAB and Simulink helped us obtain a complete view of the output jitter and analysis and jitter margin of the closed-loop system,” says Liu.

IDT-Newave is using MATLAB to develop algorithms for high-speed serial transmission, which will help them develop cutting-edge, gigabit data-transceiver products.