HDL Implementation and Verification of a High-Performance FFT

Learn how to implement and verify a high-speed signal processing algorithm using HDL Coder and HDL Verifier.

High-speed signal processing is a requirement for application such as radar, broadband wireless and backhaul. This webinar illustrates the workflow for designing a 1.6 giga-samples per second (GSPS) fast Fourier transform (FFT) algorithm and implementing it on an FPGA.

The demonstration will include:

• Developing a high-level radix-4 4096-point FFT algorithm in MATLAB.
• Building the hardware implementation model in Simulink.
• Converting the implementation to fixed-point.
• Optimizing for the target FPGA device.
• Generating synthesizable VHDL using HDL Coder that achieves 1.6 GSPS with only 60 multipliers.
• Verifying the generated VHDL using HDL Verifier.