Jack Erickson, MathWorks
In production, FPGA, ASIC, and SoC projects, RTL verification typically consumes the most time and effort of any task. Despite this effort, bugs still make it into silicon at a higher rate than desired. One of the root causes is the communication gap between algorithm design, which often starts in MATLAB® or Simulink®, and RTL design and verification. New algorithms are too complicated to rely on specification documents and hand-writing code.
This video presents a solution to this communication gap, presented in the order in which we typically see our customers adopt these new techniques:
This phased approach to adoption yields benefits for the verification team almost immediately, and over the long term encourages collaboration between system/algorithm design, hardware design, and hardware verification, leading to a more robust and agile development process.
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