Performance, Power, and Area Optimizations
R2026bMeet the timing and area requirements of your target hardware by using these HDL optimizations:
Area optimizations reduce the resource usage of the design.
Performance optimizations improve the timing of the design on the target FPGA so that the design runs at higher frequencies.
I/O optimizations reduce the I/O for algorithms that use large inputs.
Additionally, HDL Coder provides optimizations that help you balance speed, area, throughput, and latency. For more information on optimization techniques, see Introduction to Optimizations in HDL Coder and Enabling Optimizations in HDL Coder.
| Optimization | Technique |
|---|---|
| Area | Resource Sharing |
| Streaming | |
| Loop Streaming | |
| RAM Mapping | |
| Performance | Clock-Rate Pipelining |
| Distributed Pipelining | |
| Adaptive Pipelining | |
| Loop Unrolling | |
| I/O | Frame to Sample Conversion |
Categories
- Pipelining
Optimize speed by using adaptive pipelining, clock-rate pipelining, and distributed pipelining
- Delay Balancing
Insert matching delays on parallel signal paths
- Critical Path Estimation
Find estimated critical paths
- Resource Sharing and Streaming
Optimize area on target hardware
- RAM Mapping
Map large delays, persistent variables in MATLAB code, and pipeline delays to RAM
- Frame to Sample Conversion
I/O improvements using frame-to-sample conversion, multiple sampling handling, and I/O thresholding
- MATLAB Loop Optimization
Optimize loops in MATLAB code
- Constant Multiplier Optimization
Optimize area by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques
- General Optimizations
Hierarchy flattening, constrained overclocking, and feedback loop highlighting
Featured Examples
Use Multicycle Path Constraints to Meet Timing for Slow Paths
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see Enable-Based Multicycle Path Constraints.
Use Delay Absorption While Modeling with Latency
Model with latency to absorb design delays and prevent a timing mismatch between the original and generated model.
Generate IP Core for Frame-Based Model with AXI4 Stream Interfaces
Leverage the frame to sample optimization from HDL Coder™ to generate a sample-based IP core with AXI4-Stream interfaces from a frame-based Simulink® model. The generated IP core can then be deployed to hardware and verified using live streaming data from MATLAB®.
Distributed Pipelining: Speed Optimization
Optimize a Simulink® design for speed by using the distributed pipelining optimization.
